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ASAHI KASEI
[AK2504A]
AK2504A
DS3/STS-1/E3 Transceiver
GENERAL DESCRIPTION
The AK2504A is a DSP based line transceiver. It provides the analog transmit/receive line interface functions for DS3(44.736MHz) /STS-1(51.84MHz) or E3(34.368MHz) interface. Transmitter includes on-chip pulse shaper, B3ZS/ HDB3 Encoder. Pulse level adjustment function is very useful to put a pulse into pulse mask for any customer's system. Receiver includes root-f equalizer, automatic-gain control, clock and data recovery, B3ZS/HDB3 Decoder, Loss-Of-Signal and Loss-Of-Lock alarm function. Local and Remote Loop-back function is included for system level trouble shooting. The device operates at a single +3.3 Volt supply and is transparent to the framing format. -
FEATURE
"Robust" DSP based line transceiver Provides Complete Analog Line Transmitter and Receiver function for DS3, STS-1 and E3 Applications Transmit Pulse Level Adjustment Provides Line Equalization, and Clock and Data Recovery Functions Compliance with Bellcore GR-499-CORE and GR-253-CORE, ANSI T1.102, T1.404, Compliance with ITU-T G.703 and G.823 Local/Remote Loopback functions B3ZS/HDB3 Encoder/Decoder Low voltage supply : +3.3V
-
PACKAGE
64 pin LQFP -
APPLICATIONS
Interfacing network transmission equipment such as SONET multiplexor and M13 to a DSX-3 cross connect. Interfacing equipment. E3 network transmission
-
-
Interfacing customer premises equipment to a line.
MS0143-E-01
-1-
2004/01
ASAHI KASEI
[AK2504A]
BLOCK DIAGRAM
RESET 61
E3 43
LBO 60
TAOS 35
PLA 56
TPDATA TNDATA TCLK
24 25 23 B3ZS/HDB3 ENCODER LOOP BACK PULSE SHAPER OUTPUT DRIVER
39
TTIP
37
TRING
14 CLOCK RECOVERY 51 7
RLOL EXCLK EQDIS
NRZ TCKPOL RCKPOL RCLK RPDATA RNDATA /LCV TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7
3 6 41 20 21 22 B3ZS/HDB3 DECODER
MUX
DATA RECOVERY
45 GAIN and LINE EQUALIZATION 44 36
RTIP RRING VDDT VSST VSST VDDA VDDV VSSV VDDP VSSP VDDB VSSB
46 9 27 26 19 58 40
29 TEST CIRCUIT LOS LOGIC 38 59 52 53 4 5 54 57
11
12
13 VSSD
8
10
42 LOSTHR
62 RLOS
30
28
55
VSSS VDDD
RLOOP LLOOP
TCAP1 TCAP2 IREF
MS0143-E-01
-2-
2004/01
ASAHI KASEI
[AK2504A]
PIN LOCATION
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33
NC NC TEST1 RTIP RRING E3 LOSTHR RCKPOL TEST7 TTIP VSST TRING VDDT TAOS NC NC
NC NC EQDIS VDDV VSSV VDDB IREF PLA VSSB TEST6 VDDA LBO RESET RLOS NC NC
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
NC NC TCAP1 VSST TCAP2 TEST3 TEST4/eTX TNDATA TPDATA TCLK RNDATA/LCV RPDATA RCLK TEST5 NC NC
NC: No Connection. Leave these pins open.
MS0143-E-01
NC NC NRZ VDDP VSSP TCKPOL EXCLK RLOOP TEST2 LLOOP VSSS VDDD VSSD RLOL NC NC
-3-
2004/01
ASAHI KASEI
[AK2504A]
PIN CONDITION
No. 3 4 5 6 7 8 9 10 11 12 13 14 19 20 21 22 23 24 25 26 27 28 29 30 Pin Name NRZ VDDP VSSP TCKPOL EXCLK RLOOP TEST2 LLOOP VSSS VDDD VSSD RLOL TEST5 RCLK RPDATA RNDATA /LCV TCLK TPDATA TNDATA TEST4 TEST3 TCAP2 VSST TCAP1 I/O I I I I I I O I O O O I I I O I O O Analog Note 1 CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS CMOS Analog Note 1 15pF 15pF 15pF "H" "L" "L" 15pF "H" CMOS CMOS CMOS CMOS CMOS Pin Type CMOS Maximum AC load Minimum DC load Status on Reset
Remarks
Note: *) NC pin number : No. 1, 2, 15, 16, 17, 18, 31, 32 NC: No Connection. Leave these pins open. 1)External capacitor (0.1 uF) is connected to VSS.
MS0143-E-01
-4-
2004/01
ASAHI KASEI
[AK2504A]
No. 35 36 37 38 39 40 41 42 43 44 45 46 51 52 53 54 55 56 57 58 59 60 61 62
Pin Name TAOS VDDT TRING VSST TTIP TEST7 RCKPOL LOSTHR
E3
I/O I O O O I I I I I I I O O I I I O
Pin Type CMOS Analog Analog CMOS CMOS Analog CMOS Analog Analog CMOS CMOS
Maximum AC load
Minimum DC load
Status on Reset
Remarks
Hi-Z Hi-Z
RRING RTIP TEST1 EQDIS VDDV VSSV VDDB IREF PLA VSSB TEST6 VDDA LBO
RESET
Analog Analog CMOS CMOS CMOS CMOS 15pF "H"
Note 2 Note 3
Note 4
RLOS
Note *)NC pin number : No. 33, 34, 47, 48, 49, 50, 63, 64 NC: No Connection. Leave these pins open. 2)External resister 4.7 k1% should be connected between IREF and VSS. 3)External resister should be connected between PLA and VSS. Normally 1.33k is connected for DS3/STS-1 or 1.27k for E3. 4)Pulled up to VDD with internal register. (typical 50k )
MS0143-E-01
-5-
2004/01
ASAHI KASEI
[AK2504A]
PIN DESCRIPTION
Receive No. Pin Name 42 LOSTHR I/O I Function Loss of Signal Threshold Control (See Table 15) The voltage forced on this pin controls the input loss-of-signal threshold. Two settings are provided by forcing VSS or VDD. Receive PLL Loss-of-Lock Active High alarm. If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High. Receive Tip Input Receive input for differential AMI signal. Requires a 1:1 transformer. Receive Ring Input Receive input for differential AMI signal. Requires a 1:1 transformer. Receive Loss-of-Signal. This pin is set high on loss of the incoming signal at RIN. External Reference Clock. A valid DS3/STS-1/E3 clock must be provided at this input. The EXCLK frequency determines the operating frequency of the device. Recovered Clock. Receive Negative Data/Line Code Violation Indicator This pin's function depends on the input level. NRZ = Low : Receive Negative Data output NRZ = High : Bipolar Violation Output 1 bit period of High level signal is output if a bipolar violation not corresponding to the appropriate coding rule or a code error is detected in the incoming data stream. The violation pulse corresponding to the appropriate coding rule is removed from the incoming data. Receive Positive Data This pin's function depends on the input level. NRZ = low : Receive Positive Data output NRZ = high : NRZ data output RCLK Polarity select. RCKPOL=L : Received data is output on the rising edge of RCLK. RCKPOL=H : Received data is output on the falling edge of RCLK. Equalizer Disable. When EQDIS=H, Equalizer is disable. Power Supply for ADC. Power Supply for VGA. Ground for VGA. Ground for PLL. Power Supply for PLL. 0 volts. +3.3 volts. 0 volts. +3.3 volts. +3.3 volts. +3.3 volts
14 45 44 62 7 20
RLOL RTIP RRING RLOS EXCLK RCLK
O I
O I O
22
RNDATA /LCV
O
21
RPDATA
O
41 51 59 52 53 4 5 54 57
RCKPOL EQDIS VDDA VDDV VSSV VDDP VSSP VDDB VSSB
I I -
0 volts.
Power Supply for Bandgap Reference. Ground for Bandgap Reference.
MS0143-E-01
-6-
2004/01
ASAHI KASEI
[AK2504A]
Transmit No. Pin Name 24 TPDATA
I/O I
25
TNDATA
I
23
TCLK
I
6 39 37
TCKPOL TTIP TRING
I O O
Function Transmit Positive Data/NRZ data This pin's function depends on the input level. NRZ = Low : Positive AMI data output NRZ = High : NRZ data Transmit Negative Data This pin's function depends on the input level. NRZ = Low : Negative AMI data output NRZ = High : Should be tied to VSS Transmit Clock TPDATA and TNDATA are sampled on the rising or falling edge of TCLK. Sampling edge must be assigned by TCKPOL pin. TCLK Polarity select. TCKPOL=Low : Transmit data is sampled on the rising edge of TCLK. TCKPOL=High : Transmit data is sampled on the falling edge of TCLK. Transmit Tip / Ring Output AMI signal output. Requires a 1:1CT transformer. Hi-Z when RESET = Low. Pulse Level Adjustment Transmit pulse level can be adjusted by the external resister. Normally 1.33k is connected for DS3/STS-1 or 1.27k for E3. If the signal power level is larger than a requirement, you can tweak it by increasing the value of this resister. NRZ mode Enable Active High input enables NRZ data interface with TPDATA and RPDATA. NRZ 0 1 TPDATA TNDATA Positive Negative NRZ (VSS) RPDATA RNDATA Positive Negative NRZ LCV
56
PLA
I
3
NRZ
I
In NRZ mode, TNDATA should be tied to VSS and RNDATA indicates LCV. Line Built Out If LBO is set to High, Line Built Out function is enable. 60 LBO I LBO input Low High Cable length 225 - 450ft 0 - 225ft
30 28 35 36 29, 38
TCAP1 TCAP2 TAOS VDDT VSST
O O I -
This pin is active only with E3 pin set to High(DS3/STS-1 mode). Reference Voltage Output for the TX driver. An external capacitor (0.1F20%) should be connected to VSSA. Reference Voltage Output for the TX driver. An external capacitor (0.1F20%) should be connected to VSSA. Transmit All Ones Select Active High input. A continuous AMI all 1's pattern to be transmitted from TTIP and TRING. Transmit rate is defined by TCLK. Power Supply for Transmitter. +3.3 volts. Ground for Transmitter. 0 volts
MS0143-E-01
-7-
2004/01
ASAHI KASEI
[AK2504A]
Others No. Pin Name 43 55 8
E3
I/O O I
IREF RLOOP
10 61
LLOOP
RESET
I I
46 9 27 26 19 58 40 12 13 11
TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 VDDD VSSD VSSS
I I I O I I O -
Function DS3/STS-1 or E3 select pin High : DS3/STS-1 Low : E3 Current Reference Output External resistance (4.7 k1%) should be connected to VSSA. Remote Loop Back Active High input. RPDATA and RNDATA are transmitted from TTIP and TRING using RCLK. Input High on both RLOOP and LLOOP are inhibited. Local Loop Back Active High input. TPDATA,TNDATA and TCLK are looped back to RPDATA, RNDATA and RCLK. Input High on both RLOOP and LLOOP are inhibited. Active low RESET. Pulled up to VDD with internal resister. Test Mode. Should be connected to VSS. TEST1=High : The part goes into Test mode. TEST1=Low : The part goes into the Normal operation mode. Should be connected to VSS. Should be connected to VSS. Output "Low" when TEST1=Low (Normal operation mode) Should be connected to VSS. Should be connected to VSS. Should be open. Power Supply for Digital. Ground for Digital. Ground for Substrate. +3.3 volts. 0 volts 0 volts
MS0143-E-01
-8-
2004/01
ASAHI KASEI
[AK2504A]
FUNCTIONAL DESCRIPTION
The AK2504A provides the basic transmit and receive functions of a high-speed line card.
Signal Requirements
DS3/STS1 Pulse characteristics are specified at the DSX-3. Table 1. DS3 Interface Specification Parameter Line Rate Line Code Test Load Standards 44.736Mbps20ppm B3ZS 755% GR-499-CORE , ANSI T1.102 , T1.404 Specification
Table 2. STS-1 Interface Specification Parameter Line Rate Line Code Test Load Standards 51.840Mbps20ppm B3ZS 755% GR-253-CORE , ANSI T1.102 Specification
MS0143-E-01
-9-
2004/01
ASAHI KASEI
[AK2504A]
1.2 1.0 Normalized Amplitude
Normilized Amplitude
1.2 1 0.8 0.6 0.4 0.2 0 -0.2 -1.00
0.8 0.6 0.4 0.2 0.0 -0.2 -1.0 -0.5 0.0 Time[UI] 0.5 1.0 1.5
-0.50
0.00 Time[UI]
0.50
1.00
1.50
Fig. 1 DSX-3 Pulse Mask
Fig. 2 STS-1 Pulse Mask
Table 3. DS3 Pulse Mask and Equations (ANSI T1.102, T1.404, GR-499-CORE)
Lower Curve Upper Curve
Time -0.85 T -0.36 -0.36 T 0.36 0.36 T 1.4
Equation -0.03 0.5{1+sin[(/2)(1+T/0.18)]}-0.03 -0.03
Time -0.85 T -0.68 -0.68 T 0.36 0.36 T 1.4
Equation 0.03 0.5{1+sin[(/2)(1+T/0.34)]}+0.03 0.08+0.407e-1.84(T-0.36)
Table 4 STS-1 Pulse Mask and Equations (GR-253-CORE, T1.102)
Lower Curve Upper Curve
Time -0.85 T -0.36 -0.36 T 0.36 0.36 T 1.4
Equation -0.03 0.5{1+sin[(/2)(1+T/0.18)]}-0.03 -0.03
Time -0.85 T -0.68 -0.68 T 0.26 0.26 T 1.4
Equation 0.03 0.5{1+sin[(/2)(1+T/0.34)]}+0.03 0.1+0.61e-2.4(T-0.26)
MS0143-E-01
- 10 -
2004/01
ASAHI KASEI
[AK2504A]
E3 Pulse characteristics are specified at the output ports Table 5. E3 Pulse Specification (G.703)
Pulse shape (nominally rectangular) Pair(s) in each direction Test load impedance Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the amplitudes of positive and negative pulses at the center of a pulse interval Ratio of the widths of positive and negative pulses at the nominal half amplitude All marks of a valid signal must conform with the mask (see Fig.3), irrespective of the sign One coaxial pair 75 s resistive 1.0 V 0 V 0.1 V 14.55 ns 0.95 to 1.05 0.95 to 1.05
17 ns (14.55 + 2.45) V 0.2
0.1
1.0
0.1
0.2
8.65 ns (14.55 - 5.90) Nominal pulse 14.55 ns
0.5
12.1 ns (14.55 - 2.45)
24.5 ns 0.1 (14.55 + 9.95) 0 0.1 0.1 29.1 ns (14.55 + 14.55)
T1818860-92
0.1
0.2
FIGURE 17/G.703
Pulse mask at the 34 368-kbit/s interface
Fig. 3 E3 Pulse Mask
MS0143-E-01
- 11 -
2004/01
ASAHI KASEI
[AK2504A]
Logic Data Interface
AK2504A can handle Positive/Negative data and NRZ data. Positive/Negative data Interface If NRZ pin = Low, the transmitter accepts Positive/Negative transmit data on TPDATA/TNDATA and the receiver outputs Positive/Negative received data on RPDATA/RNDATA. In this mode, B3ZS/HDB3 Encoder/Decoder is disable. Transmit and Received data is output transparently. NRZ data Interface If NRZ pin = High, the transmitter accepts NRZ transmit data on TPDATA (TNDATA should be tied to VSS). The receiver outputs NRZ received data on RPDATA. In this mode, B3ZS/HDB3 Encoder/Decoder is enable. LCV alarm will be indicated on RNDATA whenever a bipolar violation is detected in the incoming data stream.
Low NRZ Disable TPOS TNEG RPOS RNEG TPDATA TNDATA RPDATA RNDATA B3ZS HDB3 Encoder Decoder TNRZ TPDATA TNDATA RNRZ BPV RPDATA RNDATA High NRZ Enable B3ZS HDB3 Encoder Decoder
Positive/Negative AMI
NRZ
Fig. 4 Logic Data Interface
Line Code Violation
If a bipolar violation not corresponding to the appropriate coding rule or a code error is detected in the incoming data stream, LCV is set high for one bit period. The violation pulse corresponding to the appropriate coding rule is removed from the incoming data. Bipolar Violation B3ZS, HDB3 : HDB3: B, V B, 0, V (+1,+1) or (-1,-1) (+1, 0,+1) or (-1, 0,-1) RPDATA --LCV --RPDATA LCV ----1, 1 0, 1 1, 0, 1 0, 0, 1
Coding Violation (With an even number of Bs since the last V) B3ZS : HDB3: 0, V 0, 0, V ( 0,+1) or ( 0,-1) ( 0, 0,+1) or ( 0, 0,-1) RPDATA --LCV --RPDATA --LCV --0, 1 0, 1 0, 0, 1 0, 0, 1
MS0143-E-01
- 12 -
2004/01
ASAHI KASEI
[AK2504A]
Excessive Zeros B3ZS : HDB3: 0, 0, 0 0, 0, 0, 0 RPDATA --LCV --RPDATA --LCV --0, 0, 0 0, 0, 1 0, 0, 0, 0 0, 0, 0, 1
Receive data 0 includes B3ZS encode error
1
0
0
V1
1
1
0
V1
V0
0
1
1
0
V0
0
0
1
AMI
Bipolar violation
Code violation
Excessive zeros
RPDATA LCV
0
0
0
0
0
0
Fig. 5 RPDATA and LCV outputs in NRZ mode (B3ZS)
Receive data 0 includes HDB3 encode error
1
0
0
0
V1
1
1
0
0
V1
V0
0
1
1
0
0
V0
0
0
0
1
AMI
Bipolar violation
Code violation
Excessive zeros
RPDATA LCV
0
0
0
0
0
0
0
0
Fig. 6 RPDATA and LCV outputs in NRZ mode (HDB3)
MS0143-E-01
- 13 -
2004/01
ASAHI KASEI
[AK2504A]
Pulse Shaper
Pulse Shaper generates a waveform meeting the pulse mask such as described in Table 3,4,5. The input data of Pulse Shaper is the sampled data of TPDATA and/or TNDATA pins on the rising or falling edge of TCLK. Polarity of TCLK is selected by TCKPOL pin.
Line Built Out
When LBO = High, the transmit pulse is output through LBO circuit which makes transmit pulse filtered with the frequency response equivalent to the 225ft cable. Table 6 Transmit Pulse Amplitude (DS3/STS-1) LBO Low High Cable Length 225 - 450 ft 0 - 225ft DS3, STS-1 1150mVpk(typ) 800mVpk(typ)
Note; LBO pin is active only with E3 pin set to High(DS3/STS-1 mode).
Transmit All Ones Select
If TAOS pin is high, continuos AMI 1s are transmitted from TTIP/TRING. While this All 1s pattern is transmitted, the input data on TPDATA/TNDATA are ignored. In Local Loopback mode (LLOOP pin is high), TAOS request is accepted and the input data on TPDATA/TNDATA are loopback to RPDATA/RNDATA. In Remote Loopback mode (RLOOP pin is high), TAOS request is accepted and the recoverd data is output to RPDATA/RNDATA.
Line Short Protect
If Line is short, there is no large current on the transmit output driver because that the driver is a current source drive type.
MS0143-E-01
- 14 -
2004/01
ASAHI KASEI
[AK2504A]
Equalization
DS3/STS1 The incoming data may have the loss of cable and/or flat. Cable type and length from the cross-connect are specified as shown in Table 8. Equalizer compensates appropriately for a nominal DSX-3/STS-1 pulse as attenuated by 450 feet of 728A cable. Table 8 DS3/STS-1 Cable Specification Parameter Cable Type Cable Length E3 The incoming data may have the cable loss as shown in Table 9. Equalizer compensates appropriately for a nominal E3 pulse as attenuated by the cable. Table 9 E3 Cable Specification Parameter Cable Loss 0 - 12dB Specification Remarks Fig.7-(1)(2) Specification Type 728A coaxial cable (or equivalent) 0 - 450 feet (from DSX-3 point) Fig.7-(1)(2) Remarks
Equalizer Bypass
If the incoming signal is attenuated by flat loss only (zero cable loss), the internal equalizer should be bypassed with EQDIS=1. The level of the incoming signal should satisfy the RIN input range (50mVpk - 1000mVpk for DS3/STS-1, 90mVpk - 1200mVpk for E3). Table 10 Equalizer Bypass Control EQDIS 0 1 Equalizer Enable Bypass
Flat Loss (1)Cable loss + Flat loss Cable 0 - 6dB AK2504
EQDIS
DS3 : DSX-3 STS-1 : DSX-3 E3 : Transmitter Port (2) Flat loss only
DS3 :0 - 450 feet STS-1:0 - 450 feet E3 :0 - 12 dB
0 Equalizer enable
Flat Loss Transmitter
Monitoring circuit
AK2504
EQDIS
1 Equalizer bypass
Fig. 7 AK2504A Application MS0143-E-01 - 15 2004/01
ASAHI KASEI
[AK2504A]
Clock Acquisition
If a valid input signal is assumed to be already present at the analog input, the maximum time between the application of device power and error-free operation is typically 20 ms. Table 11 PLL Lock Acquisition Time
(TA = Tmin to Tmax; V+ = 3.3V0.3V; GND** = 0V)
Power up Input data restore
Conditions Power : Off -> On Input data : Valid Power : On Input data : Loss -> Valid
min
typ 20 1.0
Max
Units ms
5.0
ms
**) GND=VSSP= VSSV= VSSB=VSST=VSSS=VSSD=0V
Output Jitter
Typical output jitter characteristics is shown in the table of ANALOG SPECIFICATIONS .
Jitter Transfer
Jitter transfer characteristics is shown in the table of ANALOG SPECIFICATIONS.
Jitter Tolerance
Typical jitter tolerance characteristics is shown in the table of ANALOG SPECIFICATIONS. DS3/STS-1 Compliance with GR-499-CORE, GR-253-CORE, G.752, G.824 E3 Compliance with ITU-T G.823.
MS0143-E-01
- 16 -
2004/01
ASAHI KASEI
[AK2504A]
Loopback
AK2504A has two loopback modes, which are Remote Loopback mode and Local Loopback mode. Each function of those is shown in Table 12 and Fig. 8. Table 12 Loopback Function Mode Remote Local RLOOP 1 0 1 LLOOP 0 1 1 RPDATA RNDATA TPDATA TNDATA TCLK TTIP TRING RPDATA RNDATA RCLK Function Transmit rate is determined by RCLK. TPDATA/TNDATA are ignored. Transmit rate is determined by TCLK. TPDATA/TNDATA are ignored.
Not permitted that both RLOOP and LLOOP are high.
LOOP BACK MUX
Remote LoopBack
RLOOP=1 LLOOP=0
TPDATA TNDATA TCLK
B3ZS/HDB3 ENCODER PULSE SHAPER OUTPUT DRIVER
TTIP TRING
RPDATA RNDATA/BPV RCLK
B3ZS/HDB3 ENCODER
CLOCK&DATA RECOVERY
RTIP RRING
RLOOP LLOOP
LOOP BACK MUX
Local LoopBack
RLOOP=0 LLOOP=1
TPDATA TNDATA TCLK
B3ZS/HDB3 ENCODER PULSE SHAPER OUTPUT DRIVER
TTIP TRING
RPDATA RNDATA/BPV RCLK
B3ZS/HDB3 ENCODER
CLOCK&DATA RECOVERY
RTIP RRING
RLOOP LLOOP
Fig. 8 Loopback Path
MS0143-E-01
- 17 -
2004/01
ASAHI KASEI
[AK2504A]
TX and RX Output status related to NRZ, TAOS, RLOOP, LLOOP input
Table 13 TX and RX Output status E3B X 0 1 X 0 1 X 0 1 X 0 1 X X 0 1 NRZ TAOS RLOO LLOO TTIP/TRING P P 0 1 1 0 AMI ones 1 1 1 0 AMI ones 1 1 1 0 AMI ones 0 0 1 0 Recovered data 1 0 1 0 Recovered data 1 0 1 0 Recovered data 0 1 0 1 AMI ones 1 1 0 1 AMI ones 1 1 0 1 AMI ones 0 0 0 1 TPDATA/TNDATA 1 0 0 1 TPDATA/TNDATA(HDB3) 1 0 0 1 TPDATA/TNDATA(B3ZS) X 1 0 0 AMI ones 0 0 0 0 TPDATA/TNDATA 1 0 0 0 TPDATA/TNDATA(HDB3) 1 0 0 0 TPDATA/TNDATA(B3ZS) RPDATA/RNDATA Recovered data Recovered data(UNHDB3) Recovered data(UNB3ZS) Recovered data Recovered data(UNHDB3) Recovered data(UNB3ZS) TPDATA/TNDATA TPDATA/TNDATA(UNHDB3) TPDATA/TNDATA(UNB3ZS) TPDATA/TNDATA TPDATA/TNDATA(UNHDB3) TPDATA/TNDATA(UNB3ZS) Recovered data Recovered data Recovered data(UNHDB3) Recovered data(UNB3ZS)
Loss-of-Lock Detection
If the recovered clock frequency is larger than approximately 0.5% of EXCLK, RLOL alarm goes High.
External Reference Clock
An external reference clock EXCLK is used to set the frequency of the PLL. The frequency of EXCLK should be within the ideal clock100ppm.
Reset
AK2504A goes into RESET status if RESET input is low. Output pins status is as follows during the low input on RESET . RLOS : RLOL : RPDATA : RNDATA : RCLK : High High Low Low High
Test Mode
The AK2504A goes into Test Mode when TEST1 pin is High.
MS0143-E-01
- 18 -
2004/01
ASAHI KASEI
[AK2504A]
Loss of Signal DS3/STS-1
AK2504A detects the loss of signal by analog and digital methods. Loss of Signal function in DS3/STS-1 mode is as follows. Analog Loss of Signal(ALOS) Analog loss detector operates as follows. - Analog loss detector monitors the peak level of the incoming signal. - If the peak level falls below Alarm set threshold as shown in Table 14, output pins status is shown in the diagram below.
Table 14 Analog Loss-of-Signal thresholds (DS3/STS-1/E3) LOSTHR Voltage VSS VDD Clear Alarm Level Min. Upper Threshold 80 50 Max. Upper Threshold 160 110 Set Alarm Level Min. Lower Threshold 70 40 Max. Lower Threshold 150 100 Units mVpk mVpk
Notes: - Set Alarm Level is 0.5dB lower than Clear Alarm Level. Digital Loss of Signal(DLOS) Digital loss detector operates as follows. - A digital loss detector monitors consecutive 0s and 1s density in recovered data. - RLOS is set high if 1755 consecutive 0s is detected. - RPDATA,RNDATA are set low if ALOS is detected. - RLOS is set low if 33% 1s density (58 1s in 175 consecutive bits) and no consecutive 100 0s are detected.
MS0143-E-01
- 19 -
2004/01
ASAHI KASEI
[AK2504A]
Normal Operation
RCLK : Recovered from RIN data RPDATA : Recovered data RNDATA : Recovered data RLOS : Low 175bits of the incoming data includes the following data. 1) 58bits of 1s (33% 1s density) 2) No 100bits of consecutive 0s
175 +/- 5 bits of consecutive 0s in the incoming data
DLOS
RCLK : Recovered from RIN data RPDATA : Recovered data RNDATA : Recovered data RLOS Peak level of the incoming data Set Alarm Threshold < Level : High
Peak level of the incoming data
Clear Alarm Threshold > Level
ALOS
RCLK : Recovered from EXCLK RPDATA : Low RNDATA : Low RLOS : High
Fig. 9 Loss of Signal state diagram (DS3/STS-1)
MS0143-E-01
- 20 -
2004/01
ASAHI KASEI
[AK2504A]
Loss of Signal E3
AK2504A detects the loss of signal by analog and digital methods. Loss of Signal function in E3 mode is as follows. -
Analog loss detector monitors the peak level of the incoming signal. If the peak level falls below Set Alarm Threshold Level as shown in Table 15, DLOS circuit starts counting the number of the incoming data bits as described in the following section "DLOS". If DLOS circuit detects consecutive 1285 bits of the incoming data lower than Set Alarm Threshold Level, AK2504A alarms Loss of Signal by setting RLOS high. Other output pins status is as shown in the diagram below. RLOS is set low if 325 bits of the incoming data higher than Clear Alarm Threshold Level are detected.
-
-
Normal Operation
RCLK : Recovered from RIN input RPDATA : Recovered data RNDATA : Recovered data RLOS : Low
Peak level of the incoming data
Set Alarm Threshold < Level
Peak level of the incoming data
Set Alarm Threshold > Level
for 128 +/- 5 consecutive bits of the incoming data
for 32 +/- 5 bits of the incoming data
LOS
RCLK : Recovered from EXCLK RPDATA : Low RNDATA : Low RLOS : High
Fig. 10 Loss of Signal state diagram (E3)
MS0143-E-01
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ASAHI KASEI
[AK2504A]
ABSOLUTE MAXIMUM RATINGS
Parameter DC Supply (referenced to GND) (Note 1) Input Voltage, Any Pin Input Current, Any Pin (Note 2) Ambient Operating Temperature Storage Temperature Power Dissipation Symbol V+ Vin Iin TA Tstg PD Min -0.3 GND-0.3 -40 -65 Max 4.6 (V+)+0.3 10 85 150 1 Units V V MA C C W
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Note; 1.GND=VSSV=VSSP=VSSB=VSST=VSSD=VSSS=0V 2.Transient currents of up to 100 mA will not cause SCR latch up.
RECOMMENDED OPERATING CONDITIONS
Parameter DC Supply (referenced to GND) Ambient Operating Temperature Supply Current: DS3 STS-1 E3 EXCLK Frequency DS3 IS Symbol V+ Condition Min 3.0 Typ 3.3 Max 3.6 Units V C mA mA mA MHz
TA PN20 PN20 PN20
-40 44.736 - 100ppm 51.84 - 100ppm 34.368 - 100ppm
25 200 210 160 44.736
85 220 230 180 44.736 + 100ppm 51.84 + 100ppm 34.368 + 100ppm
STS-1 E3
51.84 34.368
MHz MHz
MS0143-E-01
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ASAHI KASEI
[AK2504A]
RECEIVER
ANALOG SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V0.3V; GND = 0V)
Parameter
Condition
Min -
Typ 205 0.05 20 15 2 0.6 0.4
Max 0.1
Units
kHz dB Uipp Uipp Uipp Uipp Uipp
Jitter Transfer 3dB Bandwidth with repetitive 100 pattern (Note 3) Peaking Jitter Tolerance 5kHz 10kHz 60kHz
(Note 4)
300kHz 1MHz All one's pattern Repetitive 1000 pattern 45 DS3/STS1 E3 50 90 170 123
Signal Noise Immunity Output Jitter
(Note 5) (Note 3)
8 1.4 1.8 175 128
12 55 1000 1200 180 133 8
dB nsp-p nsp-p % mVpk mVpk bits bits bits
Output Clock Duty Cycle Receiver Input Range
(Note 3)
DLOS detection Loss Detection RIN to RPDATA Delay Time
DS3/STS1 E3
Note; 3. Measured with repetitive input at nominal DSX-3 level(DS3/STS-1), nominal G.703 level(E3) with (V+)=3.3V, TA=25C 4. Typical performance is shown in Fig 11. 5. Measured with sinusoidal noise, peak amplitude of noise is 11dB down from peak amplitude of signal. The noise frequency is 22MHz(DS3), 25MHz(STS-1), 17MHz(E3).
100
3 .2 k , 1 4 U Ip p 10 G .7 5 2 G R - 4 9 9 C a te g o r y II G R - 4 9 9 C a te g o r y I
Jitter Amplitude [UIpp]
1
3 0 0 k , 0 .3 U Ip p 0 .1 0 .0 5 U Ip p
0 .0 1 0 .0 1 0 .1 1 10 100 1000 10000
J itte r F r e q u e n c y [ k H z ]
Fig. 11 Jitter Tolerance
MS0143-E-01
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ASAHI KASEI
[AK2504A]
TRANSMITTER
ANALOG SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V0.3V; GND = 0V)
Parameter Transmitter amplitude (Note 6) E3 DS3/STS1
Condition LBO=1 LBO=0
Min 700 1050 920
Typ 800 1150 1000
Max 900 1250 1080
Units
mVpk mVpk mVpk
Note; 6. Measured at the line side of the transformer.
DIGITAL CHARACTERISTICS
(TA = Tmin to Tmax; V+ = 3.3V0.3V; GND = 0V) Parameter High-Level Input Voltage Low-Level Input Voltage High-Level Output Voltage IOUT=-40A Low-Level Output Voltage Input Leakage Current IOUT=1.6mA (Note 7) IOUT=0.4mA (Note 8)
(Note 9)
Symbol VIH VIL VOH VOL
Min (V+) x 0.7 GND (V+) x 0.8 GND
Typ -
Max (V+) 0.5 (V+) 0.4 10
Units V V V V A
Note; 7. RCLK, RPDATA, RNDATA 8. RLOS, RLOL, TEST4, TEST7 9. Except for RESET
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ASAHI KASEI
[AK2504A]
RECEIVER SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ ) Parameter RCLK Pulse Width RCLK Pulse Width RCLK Pulse Width DS3 STS-1 E3 Symbol Tpwh (Note 10, 11) Tpwl Tpwh (Note 12, 11) Tpwl Tpwh (Note 13, 11) Tpwl Min 10.1 10.1 8.7 8.7 13.1 13.1 45 tr tf 0 Typ 11.177 11.177 9.645 9.645 14.548 14.548 Max 12.2 12.2 10.6 10.6 16.0 16.0 55 3.5 3.5 3.5 Units ns ns ns ns ns ns % ns ns ns
EXCLK Duty Cycle (EXCLK Min Rise/Fall time : 5ns) Rise Time, RCLK Fall Time, RCLK
(Note 11) (Note 11)
Delay Time: RCLK high to RPDATA/RNDATA (Note 14) Tdcrd
TRANSMITTER SWITCHING SPECIFICATIONS
(TA = Tmin to Tmax; V+ = 3.3V0.3V; GND = 0V; Input: Logic 0 = 0V, Logic 1 = V+ ) Parameter TCLK Duty Cycle (TCLK Min Rise/Fall time : 5ns) Rise Time, TCLK Fall Time, TCLK
(Note 11) (Note 11)
Symbol
Min 30
Typ -
Max 70 3.5 3.5 -
Units % ns ns ns ns
tr tf Tstdc Thtdc
4 5
Setup Time, TPDATA/TNDATA to TCLK Falling Hold Time, TPDATA/TNDATA to TCLK Falling
Note; 10. 11. 12. 13. 14.
Assumes PLL is locked to 44.736 MHz signal. The sum of the pulse widths must always meet the frequency specifications. Assumes PLL is locked to 51.84 MHz signal Assumes PLL is locked to 34.368MHz signal. Load cap = 15pF.
MS0143-E-01
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ASAHI KASEI
[AK2504A]
tr 90% RCLK 10% 90%
tf
10%
Fig. 12 Signal Rise and Fall Characteristics
t pwh t pwl
RCLK RPDATA RNDATA
t dcrd
Fig. 13 Recovered Clock and Data Switching Characteristics
tpwh1
VDD/2
EXCLK
tpw
Fig. 14 EXCLK Duty Cycle Requirements
TCLK
t sdc
t hdc
TPDATA TNDATA
Fig. 15 Transmitter Switching Characteristics
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ASAHI KASEI
[AK2504A]
Application Circuit Example
Note :
Leave the following NC pins open. Pin 1,2,15,16,17,18,31,32,33,34,47,48,49,50,63,64.
Recommended Diode :
Any diode with V(forward) = 0.58V to 0.89V for I(forward)=10mA in all temperature range can be used. e.g. 1SS184, 1SS181
3.3V 23 24 25 20 FRAMER 21 22 6 41 3 CONTROL LOGIC 35 14 62 42 60 51 61 8 10 43 46 9 27 Open 26,40 19 58 CLOCK SOURCE 7 TCLK TPDATA TNDATA RCLK RPDATA RNDATA TCKPOL RCKPOL NRZ TAOS RLOL RLOS LOSTHR LBO EQDIS VSSV VDDP VSSP VDDV 52 53 4 5 54 57 36 VDDA 59 RRING TRING 37 39 38 TTIP 39 39
1CT : 1
150 nH 75
AK2504A
VSST
0.1 uF COAX
RTIP
45
37.4 1:1
44 37.4 0.01 uF 3.3V 0.01 uF
0.01 uF
0.01 uF
RESET
RLOOP LLOOP
VDDB VSSB VDDT VSST
0.01 uF
E3
TEST1 TEST2 TEST3 TEST4, TEST7 TEST5 TEST6 EXCLK TCAP1 30 TCAP2 28 0.1uF
0.01 uF 29
VDDD VSSD VSSS
12 13 11 0.01 uF
Recommended Transformer :
Maker Product No. WBTRID2.5-J004C002 WBTRID2.5-0340N Ratio 1CT:1 1:1
PLA IREF 56 55 4.7 k1%
TDK TDK
0.1uF
RPLA
RPLA: 1.33k 1% for DS3/STS-1, 1.27k 1% for E3
NOTE) If the power of transmit signal is larger than the requirement, the power can be reduced by increasing the value of RPLA.
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ASAHI KASEI
[AK2504A]
Marking
- 64pin LQFP (1) Pin #1 indication (2) Date Code: 7digits XXXXYZZ (3)Marketing Code: AK2504A (4)AKM Logo
AKM
AK2504A XXXXYZZ
MS0143-E-01
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ASAHI KASEI
[AK2504A]
Outline Dimensions
12.00.3 10.0 48 33
49
32
12.00.3
10.0
64
17
1 0.5 0.210.05 1.0
16 1.70MAX
0.10
M
0-10 1.40
MS0143-E-01
0.170.05
0.450.2
0.10
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0.100.10
2004/01
ASAHI KASEI
[AK2504A]
IMPORTANT NOTICE These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
MS0143-E-01
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2004/01

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